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020 _a9783540714316
_9978-3-540-71431-6
024 7 _a10.1007/978-3-540-71431-6
_2doi
050 4 _aQA75.5-76.95
072 7 _aUYA
_2bicssc
072 7 _aCOM014000
_2bisacsh
072 7 _aUYA
_2thema
082 0 4 _a004.0151
_223
245 1 0 _aReconfigurable Computing: Architectures, Tools and Applications
_h[electronic resource] :
_bThird International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings /
_cedited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso.
250 _a1st ed. 2007.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2007.
300 _aXIV, 394 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4419
505 0 _aArchitectures [Regular Papers] -- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array -- A Configurable Multi-ported Register File Architecture for Soft Processor Cores -- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture -- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture -- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs -- Systematic Customization of On-Chip Crossbar Interconnects -- Authentication of FPGA Bitstreams: Why and How -- Architectures [Short Papers] -- Design of a Reversible PLD Architecture -- Designing Heterogeneous FPGAs with Multiple SBs -- Mapping Techniques and Tools [Regular Papers] -- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations -- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware -- Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations -- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions -- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping -- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining -- Hardware/Software Codesign for Embedded Implementation of Neural Networks -- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues -- Mapping Techniques and Tools [Short Papers] -- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations -- Arithmetic [Regular Papers] -- Switching Activity Models for Power Estimation in FPGA Multipliers -- Multiplication over on FPGA: A Survey -- A Parallel Version of the Itoh-Tsujii MultiplicativeInversion Algorithm -- A Fast Finite Field Multiplier -- Applications [Regular Papers] -- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval -- Image Processing Architecture for Local Features Computation -- A Compact Shader for FPGA-Based Volume Rendering Accelerators -- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications -- FPGA-Accelerated Molecular Dynamics Simulations: An Overview -- Reconfigurable Hardware Acceleration of Canonical Graph Labelling -- Reconfigurable Computing for Accelerating Protein Folding Simulations -- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits -- Applications [Short Papers] -- A Space Variant Mapping Architecture for Reliable Car Segmentation -- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads -- Searching the Web with an FPGA Based Search Engine -- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma -- Real Time Architectures for Moving-Objects Tracking -- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller -- Multiple Sequence Alignment Using Reconfigurable Computing -- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.
650 0 _aComputer science.
_99832
650 0 _aComputers.
_98172
650 0 _aMicroprocessors.
_9129959
650 0 _aComputer architecture.
_93513
650 0 _aComputer networks .
_931572
650 0 _aElectronic digital computers
_xEvaluation.
_921495
650 0 _aComputer systems.
_9129960
650 1 4 _aTheory of Computation.
_9129961
650 2 4 _aComputer Hardware.
_933420
650 2 4 _aProcessor Architectures.
_9129962
650 2 4 _aComputer Communication Networks.
_9129963
650 2 4 _aSystem Performance and Evaluation.
_932047
650 2 4 _aComputer System Implementation.
_938514
700 1 _aDiniz, Pedro C.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129964
700 1 _aMarques, Eduardo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129965
700 1 _aBertels, Koen.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129966
700 1 _aFernandes, Marcio Merino.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129967
700 1 _aCardoso, Joao M.P.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9129968
710 2 _aSpringerLink (Online service)
_9129969
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540714309
776 0 8 _iPrinted edition:
_z9783540836513
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v4419
_9129970
856 4 0 _uhttps://doi.org/10.1007/978-3-540-71431-6
912 _aZDB-2-SCS
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