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020 _a9783540465614
_9978-3-540-46561-4
024 7 _a10.1007/11894063
_2doi
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_2bicssc
072 7 _aURY
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072 7 _aCOM083000
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082 0 4 _a005.824
_223
245 1 0 _aCryptographic Hardware and Embedded Systems - CHES 2006
_h[electronic resource] :
_b8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings /
_cedited by Louis Goubin, Mitsuru Matsui.
250 _a1st ed. 2006.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2006.
300 _aXII, 462 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aSecurity and Cryptology,
_x2946-1863 ;
_v4249
505 0 _aSide Channels I -- Template Attacks in Principal Subspaces -- Templates vs. Stochastic Methods -- Towards Security Limits in Side-Channel Attacks -- Low Resources -- HIGHT: A New Block Cipher Suitable for Low-Resource Device -- Invited Talk I -- Integer Factoring Utilizing PC Cluster -- Hardware Attacks and Countermeasures I -- Optically Enhanced Position-Locked Power Analysis -- Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations -- A Generalized Method of Differential Fault Attack Against AES Cryptosystem -- Special Purpose Hardware -- Breaking Ciphers with COPACOBANA -A Cost-Optimized Parallel Code Breaker -- Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware -- Efficient Algorithms for Embedded Processors -- Implementing Cryptographic Pairings on Smartcards -- SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form -- Fast Generation of Prime Numbers on Portable Devices: An Update -- Side Channels II -- A Proposition for Correlation Power Analysis Enhancement -- High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching -- Cache-Collision Timing Attacks Against AES -- Provably Secure S-Box Implementation Based on Fourier Transform -- Invited Talk II -- The Outer Limits of RFID Security -- Hardware Attacks and Countermeasures II -- Three-Phase Dual-Rail Pre-charge Logic -- Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage -- Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style -- Efficient Hardware I -- Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors -- NanoCMOS-Molecular Realization of Rijndael -- Improving SHA-2 Hardware Implementations -- Trusted Computing.-Offline Hardware/Software Authentication for Reconfigurable Platforms -- Side Channels III -- Why One Should Also Secure RSA Public Key Elements -- Power Attack on Small RSA Public Exponent -- Unified Point Addition Formulæ and Side-Channel Attacks -- Hardware Attacks and Countermeasures III -- Read-Proof Hardware from Protective Coatings -- Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits -- Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks -- Invited Talk III -- Challenges for Trusted Computing -- Efficient Hardware II -- Superscalar Coprocessor for High-Speed Curve-Based Cryptography -- Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller -- FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers.
520 _aThese are the proceedings of the Eighth Workshop on Cryptographic Hardware and Embedded Systems (CHES 2006) held in Yokohama, Japan, October 10-13, 2006. The CHES workshophas been sponsored by the International Association for Cryptographic Research (IACR) since 2004. The ?rst and the second CHES workshops were held in Worcester in 1999 and 2000, respectively, followed by Paris in 2001, San Francisco Bay Area in 2002, Cologne in 2003, Boston in 2004 and Edinburgh in 2005. This is the ?rst CHES workshop held in Asia. This year,a totalof 112 paper submissionswerereceived.The reviewprocess was therefore a delicate and challenging task for the Program Committee m- bers. Each paper was carefully read by at least three reviewers, and submissions with a Program Committee member as a (co-)author by at least ?ve reviewers. The review process concluded with a two week Web discussion process which resulted in 32 papers being selected for presentation. Unfortunately, there were a number of good papers that could not be included in the program due to a lack of space. We would like to thank all the authors who submitted papers to CHES 2006. In addition to regular presentations, we were very fortunate to have in the programthreeexcellentinvitedtalksgivenbyKazumaroAoki(NTT)on"Integer Factoring Utilizing PC Cluster," Ari Juels (RSA Labs) on "The Outer Limits of RFID Security" and Ahmad Sadeghi (Ruhr University Bochum) on "Challenges for Trusted Computing." The program also included a rump session, chaired by Christof Paar, featuring informal presentations on recent results.
650 0 _aCryptography.
_91973
650 0 _aData encryption (Computer science).
_99168
650 0 _aComputer networks .
_931572
650 0 _aComputers, Special purpose.
_946653
650 0 _aLogic design.
_93686
650 0 _aOperating systems (Computers).
_95329
650 0 _aElectronic data processing
_xManagement.
_9159955
650 1 4 _aCryptology.
_931769
650 2 4 _aComputer Communication Networks.
_9159956
650 2 4 _aSpecial Purpose and Application-Based Systems.
_946654
650 2 4 _aLogic Design.
_93686
650 2 4 _aOperating Systems.
_937074
650 2 4 _aIT Operations.
_931703
700 1 _aGoubin, Louis.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9159957
700 1 _aMatsui, Mitsuru.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9159958
710 2 _aSpringerLink (Online service)
_9159959
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540465591
776 0 8 _iPrinted edition:
_z9783540831679
830 0 _aSecurity and Cryptology,
_x2946-1863 ;
_v4249
_9159960
856 4 0 _uhttps://doi.org/10.1007/11894063
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