000 03706nam a22006135i 4500
001 978-3-642-19448-1
003 DE-He213
005 20240730195834.0
007 cr nn 008mamaa
008 110223s2011 gw | s |||| 0|eng d
020 _a9783642194481
_9978-3-642-19448-1
024 7 _a10.1007/978-3-642-19448-1
_2doi
050 4 _aQA76.9.C62
072 7 _aUK
_2bicssc
072 7 _aCOM036000
_2bisacsh
072 7 _aUK
_2thema
082 0 4 _a004.01513
_223
245 1 0 _aTransactions on High-Performance Embedded Architectures and Compilers III
_h[electronic resource] /
_cedited by Per Stenström.
250 _a1st ed. 2011.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2011.
300 _aXIV, 299 p. 171 illus., 66 illus. in color.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v6590
520 _aTransactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This third issue contains 14 papers carefully reviewed and selected out of numerous submissions and is divided into four sections. The first section contains the top four papers from the Third International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, in January 2008. The second section consists of four papers from the 8th MEDEA Workshop held in conjunction with PACT 2007 in Brasov, Romania, in September 2007. The third section  contains two regular papers and the fourth section provides a snapshot from the First Workshop on Programmability Issues for Multicore Computers, MULTIPROG, held in conjunction with HiPEAC 2008.
650 0 _aComputer arithmetic and logic units.
_936750
650 0 _aMicroprocessors.
_9161470
650 0 _aComputer architecture.
_93513
650 0 _aComputer input-output equipment.
_922942
650 0 _aLogic design.
_93686
650 0 _aComputer networks .
_931572
650 0 _aCompilers (Computer programs).
_93350
650 1 4 _aArithmetic and Logic Structures.
_936752
650 2 4 _aProcessor Architectures.
_9161471
650 2 4 _aInput/Output and Data Communications.
_937326
650 2 4 _aLogic Design.
_93686
650 2 4 _aComputer Communication Networks.
_9161472
650 2 4 _aCompilers and Interpreters.
_931853
700 1 _aStenström, Per.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9161473
710 2 _aSpringerLink (Online service)
_9161474
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783642194474
776 0 8 _iPrinted edition:
_z9783642194498
830 0 _aTransactions on High-Performance Embedded Architectures and Compilers,
_x1864-3078 ;
_v6590
_9161475
856 4 0 _uhttps://doi.org/10.1007/978-3-642-19448-1
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cELN
999 _c95798
_d95798