000 08052nam a22006615i 4500
001 978-3-540-31664-0
003 DE-He213
005 20240730202857.0
007 cr nn 008mamaa
008 100715s2005 gw | s |||| 0|eng d
020 _a9783540316640
_9978-3-540-31664-0
024 7 _a10.1007/b138322
_2doi
050 4 _aQA75.5-76.95
072 7 _aUYA
_2bicssc
072 7 _aCOM014000
_2bisacsh
072 7 _aUYA
_2thema
082 0 4 _a004.0151
_223
245 1 0 _aEmbedded Computer Systems: Architectures, Modeling, and Simulation
_h[electronic resource] :
_b5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, Proceedings /
_cedited by Timo D. Hämäläinen, Andy D. Pimentel, Jarmo Takala, Stamatis Vassiliadis.
250 _a1st ed. 2005.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2005.
300 _aXV, 476 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v3553
505 0 _aKeynote -- Platform Thinking in Embedded Systems -- Reconfigurable System Design and Implementations -- Interprocedural Optimization for Dynamic Hardware Configurations -- Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques -- Reconfigurable Multiple Operation Array -- RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration -- Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping -- Automatic FIR Filter Generation for FPGAs -- Two-Dimensional Fast Cosine Transform for Vector-STA Architectures -- Configurable Computing for High-Security/High-Performance Ambient Systems -- FPL-3E: Towards Language Support for Reconfigurable Packet Processing -- Processor Architectures, Design and Simulation -- Flux Caches: What Are They and Are They Useful? -- First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption -- A Novel JAVA Processor for Embedded Devices -- Formal Specification of a Protocol Processor -- Tuning a Protocol Processor Architecture Towards DSP Operations -- Observations on Power-Efficiency Trends in Mobile Communication Devices -- CORDIC-Augmented Sandbridge Processor for Channel Equalization -- Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic -- Exploiting Intra-function Correlation with the Global History Stack -- Power Efficient Instruction Caches for Embedded Systems -- Micro-architecture Performance Estimation by Formula -- Offline Phase Analysis and Optimization for Multi-configuration Processors -- Hardware Cost Estimation for Application-Specific Processor Design -- Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures -- Generating Stream Based Code from Plain C -- Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First -- A Programming Model for an Embedded Media Processing Architecture -- Automatic ADL-Based Assembler Generation for ASIP Programming Support -- Sandbridge Software Tools -- Architectures and Implementations -- A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems -- Pattern Matching Acceleration for Network Intrusion Detection Systems -- Real-Time Stereo Vision on a Reconfigurable System -- Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design -- Compressed Swapping for NAND Flash Memory Based Embedded Systems -- A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms -- A Scalable Embedded JPEG2000 Architecture -- A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design -- Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context -- DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor -- System Level Design, Modeling and Simulation -- Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets -- High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks -- The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models -- Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow -- Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms -- DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context -- SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC -- Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications -- A Case for Visualization-Integrated System-Level Design Space Exploration -- Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of Concept.
520 _aThe SAMOS workshop is an international gathering of highly quali?ed researchers from academia and industry, sharing in a 3-day lively discussion on the quiet and - spiring northern mountainside of the Mediterranean island of Samos. As a tradition, the workshop features workshop presentations in the morning, while after lunch all kinds of informal discussions and nut-cracking gatherings take place. The workshop is unique in the sense that not only solved research problems are presented and discussed but also (partly) unsolved problems and in-depth topical reviews can be unleashed in the sci- ti?c arena. Consequently, the workshop provides the participants with an environment where collaboration rather than competition is fostered. The earlier workshops, SAMOS I-IV (2001-2004), were composed only of invited presentations. Due to increasing expressions of interest in the workshop, the Program Committee of SAMOS V decided to open the workshop for all submissions. As a result the SAMOS workshop gained an immediate popularity; a total of 114 submitted papers were received for evaluation. The papers came from 24 countries and regions: Austria (1), Belgium (2), Brazil (5), Canada (4), China (12), Cyprus (2), Czech Republic (1), Finland (15), France (6), Germany (8), Greece (5), Hong Kong (2), India (2), Iran (1), Korea (24), The Netherlands (7), Pakistan (1), Poland (2), Spain (2), Sweden (2), T- wan (1), Turkey (2), UK (2), and USA (5). We are grateful to all of the authors who submitted papers to the workshop.
650 0 _aComputer science.
_99832
650 0 _aComputers.
_98172
650 0 _aMicroprocessors.
_9173478
650 0 _aComputer architecture.
_93513
650 0 _aComputer networks .
_931572
650 0 _aElectronic digital computers
_xEvaluation.
_921495
650 0 _aComputer systems.
_9173479
650 1 4 _aTheory of Computation.
_9173480
650 2 4 _aComputer Hardware.
_933420
650 2 4 _aProcessor Architectures.
_9173481
650 2 4 _aComputer Communication Networks.
_9173482
650 2 4 _aSystem Performance and Evaluation.
_932047
650 2 4 _aComputer System Implementation.
_938514
700 1 _aHämäläinen, Timo D.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9173483
700 1 _aPimentel, Andy D.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9173484
700 1 _aTakala, Jarmo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9173485
700 1 _aVassiliadis, Stamatis.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9173486
710 2 _aSpringerLink (Online service)
_9173487
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540269694
776 0 8 _iPrinted edition:
_z9783540812739
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v3553
_9173488
856 4 0 _uhttps://doi.org/10.1007/b138322
912 _aZDB-2-SCS
912 _aZDB-2-SXCS
912 _aZDB-2-LNC
942 _cELN
999 _c97225
_d97225