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020 _a9783540929901
_9978-3-540-92990-1
024 7 _a10.1007/978-3-540-92990-1
_2doi
050 4 _aQA76.9.S88
072 7 _aUYD
_2bicssc
072 7 _aCOM011000
_2bisacsh
072 7 _aUYD
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082 0 4 _a004.2
_223
245 1 0 _aHigh Performance Embedded Architectures and Compilers
_h[electronic resource] :
_bFourth International Conference, HiPEAC 2009 /
_cedited by André Seznec, Joel Emer, Michael O'Boyle, Margaret Martonosi, Theo Ungerer.
250 _a1st ed. 2009.
264 1 _aBerlin, Heidelberg :
_bSpringer Berlin Heidelberg :
_bImprint: Springer,
_c2009.
300 _aXIII, 420 p.
_bonline resource.
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
347 _atext file
_bPDF
_2rda
490 1 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v5409
505 0 _aInvited Program -- Keynote: Challenges on the Road to Exascale Computing -- Keynote: Compilers in the Manycore Era -- I Dynamic Translation and Optimisation -- Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering -- Predictive Runtime Code Scheduling for Heterogeneous Architectures -- Collective Optimization -- High Speed CPU Simulation Using LTU Dynamic Binary Translation -- II Low Level Scheduling -- Integrated Modulo Scheduling for Clustered VLIW Architectures -- Software Pipelining in Nested Loops with Prolog-Epilog Merging -- A Flexible Code Compression Scheme Using Partitioned Look-Up Tables -- III Parallelism and Resource Control -- MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor -- IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor -- A Hardware Task Scheduler for Embedded Video Processing -- Finding Stress Patterns in Microprocessor Workloads -- IV Communication -- Deriving Efficient Data Movement from Decoupled Access/Execute Specifications -- MPSoC Design Using Application-Specific Architecturally Visible Communication -- Communication Based Proactive Link Power Management -- V Mapping for CMPs -- Mapping and Synchronizing Streaming Applications on Cell Processors -- Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors -- Accomodating Diversity in CMPs with Heterogeneous Frequencies -- A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip -- VI Power -- Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture -- Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines -- HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic -- Compiler Controlled Speculationfor Power Aware ILP Extraction in Dataflow Architectures -- VII Cache Issues -- Revisiting Cache Block Superloading -- ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors -- In-Network Caching for Chip Multiprocessors -- VIII Parallel Embedded Applications -- Parallel LDPC Decoding on the Cell/B.E. Processor -- Parallel H.264 Decoding on an Embedded Multicore Processor.
520 _aThis book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.
650 0 _aComputer systems.
_9177028
650 0 _aComputer arithmetic and logic units.
_936750
650 0 _aMicroprocessors.
_9177029
650 0 _aComputer architecture.
_93513
650 0 _aComputer input-output equipment.
_922942
650 0 _aLogic design.
_93686
650 0 _aComputer networks .
_931572
650 1 4 _aComputer System Implementation.
_938514
650 2 4 _aArithmetic and Logic Structures.
_936752
650 2 4 _aProcessor Architectures.
_9177030
650 2 4 _aInput/Output and Data Communications.
_937326
650 2 4 _aLogic Design.
_93686
650 2 4 _aComputer Communication Networks.
_9177031
700 1 _aSeznec, André.
_eeditor.
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_9177032
700 1 _aEmer, Joel.
_eeditor.
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_9177033
700 1 _aO'Boyle, Michael.
_eeditor.
_4edt
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_9177034
700 1 _aMartonosi, Margaret.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9177035
700 1 _aUngerer, Theo.
_eeditor.
_4edt
_4http://id.loc.gov/vocabulary/relators/edt
_9177036
710 2 _aSpringerLink (Online service)
_9177037
773 0 _tSpringer Nature eBook
776 0 8 _iPrinted edition:
_z9783540929895
776 0 8 _iPrinted edition:
_z9783540929918
830 0 _aTheoretical Computer Science and General Issues,
_x2512-2029 ;
_v5409
_9177038
856 4 0 _uhttps://doi.org/10.1007/978-3-540-92990-1
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