Domain-specific processors : systems, architectures, modeling, and simulation /
edited by Shuvra Bhattacharyya, Ed Deprettere, Jurgen Teich.
- 1 online resource (xv, 261 pages)
- Signal processing and communications ; 20 .
chapter 1 Automatic VHDL Model Generation of Parameterized FIR Filters / chapter 2 An LUT-Based High Level Synthesis Framework for Recon?gurable Architectures / chapter 3 Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / chapter 4 Stride Permutation Access in Interleaved Memory Systems / chapter 5 On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / chapter 6 Energy Estimation and Optimization for Piecewise Regular Processor Arrays / chapter 7 Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / chapter 8 Goal-Driven Recon?guration of Polymorphous Architectures / chapter 9 Realizations of the Extended Linearization Model / chapter 10 Communication Services for Networks on Chip / chapter 11 Single-Chip Multiprocessing for Consumer Electronics -- chapter 12 Future Directions of Programmable and Recon?gurable Embedded Processors / E. George Walters III, John Glossner, and Michael J. Schulte -- Loi�c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen -- David Guevorkian -- Jarmo Takala and Tuomas Ja�rvinen -- Andy D. Pimentel -- Frank Hannig and Ju�rgen Teich -- Steven Derrien -- Sumit Lohani -- Alexandru Turjan -- Andrei Ra?dulescu and Kees Goossens -- Stephan Wong.
9781135522643 (e-book: PDF) 9781135522599 9781135522636
10.1201/9780203913185 doi
Embedded computer systems.
Multiprocessors.
TK7895.E42 / D66 2003
004.16 / D666
chapter 1 Automatic VHDL Model Generation of Parameterized FIR Filters / chapter 2 An LUT-Based High Level Synthesis Framework for Recon?gurable Architectures / chapter 3 Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / chapter 4 Stride Permutation Access in Interleaved Memory Systems / chapter 5 On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / chapter 6 Energy Estimation and Optimization for Piecewise Regular Processor Arrays / chapter 7 Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / chapter 8 Goal-Driven Recon?guration of Polymorphous Architectures / chapter 9 Realizations of the Extended Linearization Model / chapter 10 Communication Services for Networks on Chip / chapter 11 Single-Chip Multiprocessing for Consumer Electronics -- chapter 12 Future Directions of Programmable and Recon?gurable Embedded Processors / E. George Walters III, John Glossner, and Michael J. Schulte -- Loi�c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen -- David Guevorkian -- Jarmo Takala and Tuomas Ja�rvinen -- Andy D. Pimentel -- Frank Hannig and Ju�rgen Teich -- Steven Derrien -- Sumit Lohani -- Alexandru Turjan -- Andrei Ra?dulescu and Kees Goossens -- Stephan Wong.
9781135522643 (e-book: PDF) 9781135522599 9781135522636
10.1201/9780203913185 doi
Embedded computer systems.
Multiprocessors.
TK7895.E42 / D66 2003
004.16 / D666