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Domain-specific processors : systems, architectures, modeling, and simulation / edited by Shuvra Bhattacharyya, Ed Deprettere, Jurgen Teich.

Contributor(s): Bhattacharyya, Shuvra S, 1968- | Deprettere, Ed. F, 1944- | Teich, Jurgen, 1964-.
Material type: materialTypeLabelBookSeries: Signal processing and communications ; 20.Publisher: New York : Marcel Dekker, 2003Description: 1 online resource (xv, 261 pages).Content type: text Media type: computer Carrier type: online resourceISBN: 9781135522643 (e-book: PDF); 9781135522599; 9781135522636.Subject(s): Embedded computer systems | MultiprocessorsAdditional physical formats: Print version: : No titleDDC classification: 004.16 Online resources: Click here to view.
Contents:
chapter 1 Automatic VHDL Model Generation of Parameterized FIR Filters / E. George Walters III, John Glossner, and Michael J. Schulte -- chapter 2 An LUT-Based High Level Synthesis Framework for Recon?gurable Architectures / Loi�c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen -- chapter 3 Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / David Guevorkian -- chapter 4 Stride Permutation Access in Interleaved Memory Systems / Jarmo Takala and Tuomas Ja�rvinen -- chapter 5 On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / Andy D. Pimentel -- chapter 6 Energy Estimation and Optimization for Piecewise Regular Processor Arrays / Frank Hannig and Ju�rgen Teich -- chapter 7 Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / Steven Derrien -- chapter 8 Goal-Driven Recon?guration of Polymorphous Architectures / Sumit Lohani -- chapter 9 Realizations of the Extended Linearization Model / Alexandru Turjan -- chapter 10 Communication Services for Networks on Chip / Andrei Ra?dulescu and Kees Goossens -- chapter 11 Single-Chip Multiprocessing for Consumer Electronics -- chapter 12 Future Directions of Programmable and Recon?gurable Embedded Processors / Stephan Wong.
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chapter 1 Automatic VHDL Model Generation of Parameterized FIR Filters / E. George Walters III, John Glossner, and Michael J. Schulte -- chapter 2 An LUT-Based High Level Synthesis Framework for Recon?gurable Architectures / Loi�c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen -- chapter 3 Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms / David Guevorkian -- chapter 4 Stride Permutation Access in Interleaved Memory Systems / Jarmo Takala and Tuomas Ja�rvinen -- chapter 5 On Modeling Intra-Task Parallelism in Task-Level Parallel Embedded Systems / Andy D. Pimentel -- chapter 6 Energy Estimation and Optimization for Piecewise Regular Processor Arrays / Frank Hannig and Ju�rgen Teich -- chapter 7 Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures / Steven Derrien -- chapter 8 Goal-Driven Recon?guration of Polymorphous Architectures / Sumit Lohani -- chapter 9 Realizations of the Extended Linearization Model / Alexandru Turjan -- chapter 10 Communication Services for Networks on Chip / Andrei Ra?dulescu and Kees Goossens -- chapter 11 Single-Chip Multiprocessing for Consumer Electronics -- chapter 12 Future Directions of Programmable and Recon?gurable Embedded Processors / Stephan Wong.

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