Broadband Direct RF Digitization Receivers (Record no. 56535)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03745nam a22004815i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-3-319-01150-9 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20200421112039.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 130906s2014 gw | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9783319011509 |
| -- | 978-3-319-01150-9 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Jamin, Olivier. |
| 245 10 - TITLE STATEMENT | |
| Title | Broadband Direct RF Digitization Receivers |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XVI, 162 p. 166 illus., 68 illus. in color. |
| 490 1# - SERIES STATEMENT | |
| Series statement | Analog Circuits and Signal Processing, |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | RF Receiver Architecture State-of-the-Art -- System-Level Design Framework for Direct RF Digitization Receivers -- Application to the System Design of a Multi-Channel Cable Receiver -- Realization & Measurements -- Conclusions & Perspectives. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book discusses the trade-offs involved in designing direct RF digitization receivers for the radio frequency and digital signal processing domains.  A system-level framework is developed, quantifying the relevant impairments of the signal processing chain, through a comprehensive system-level analysis.  Special focus is given to noise analysis (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion analysis, including the impact of the sampling strategy (low-pass, band-pass), analysis of time-interleaved ADC channel mismatches, sampling clock purity and digital channel selection. The system-level framework described is applied to the design of a cable multi-channel RF direct digitization receiver. An optimum RF signal conditioning, and some algorithms (automatic gain control loop, RF front-end amplitude equalization control loop) are used to relax the requirements of a 2.7GHz 11-bit ADC. A two-chip implementation is presented, using BiCMOS and 65nm CMOS processes, together with the block and system-level measurement results. Readers will benefit from the techniques presented, which are highly competitive, both in terms of cost and RF performance, while drastically reducing power consumption.  �         Provides system-level analysis of direct RF sampling & digitization receivers, from the antenna to the digital channel selection; �         Includes analysis of broadband non-linearity, applicable for low-pass and band-pass sampling strategies; Describes system-level design of an application-optimized signal conditioner, including a single-inductance multi-slope programmable RF amplitude equalizer, together with its control algorithm and a mixed-signal AGC loop combining RMS and peak detection.  . |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-3-319-01150-9 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Cham : |
| -- | Springer International Publishing : |
| -- | Imprint: Springer, |
| -- | 2014. |
| 336 ## - | |
| -- | text |
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| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprocessors. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Signal, Image and Speech Processing. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Processor Architectures. |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| -- | 1872-082X ; |
| 912 ## - | |
| -- | ZDB-2-ENG |
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