Test Generation of Crosstalk Delay Faults in VLSI Circuits (Record no. 76215)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03419nam a22005535i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-981-13-2493-2 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20220801214323.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 180920s2019 si | s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | 9789811324932 |
| -- | 978-981-13-2493-2 |
| 082 04 - CLASSIFICATION NUMBER | |
| Call Number | 621.3815 |
| 100 1# - AUTHOR NAME | |
| Author | Jayanthy, S. |
| 245 10 - TITLE STATEMENT | |
| Title | Test Generation of Crosstalk Delay Faults in VLSI Circuits |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 1st ed. 2019. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Number of Pages | XI, 156 p. 49 illus., 7 illus. in color. |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Remark 2 | Chapter 1. Background and Review of Crosstalk Delay Fault Models and the Crosstalk Effects -- Chapter 2. Review of Test Generation Techniques for Crosstalk Delay Faults -- Chapter 3. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Modified PODEM and FAN Algorithm -- Chapter 4. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults using Single-Objective Genetic Algorithm -- Chapter 5. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Single-Objective Particle Swarm Optimization -- Chapter 6. Simulation of Asynchronous Sequential Circuits using Fuzzy Delay Model -- Chapter 7. Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing. |
| 700 1# - AUTHOR 2 | |
| Author 2 | Bhuvaneswari, M.C. |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | https://doi.org/10.1007/978-981-13-2493-2 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | eBooks |
| 264 #1 - | |
| -- | Singapore : |
| -- | Springer Nature Singapore : |
| -- | Imprint: Springer, |
| -- | 2019. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic circuits. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Microprogramming . |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Computers. |
| 650 #0 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic design. |
| 650 14 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Electronic Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Control Structures and Microprogramming. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Hardware Performance and Reliability. |
| 650 24 - SUBJECT ADDED ENTRY--SUBJECT 1 | |
| -- | Logic Design. |
| 912 ## - | |
| -- | ZDB-2-ENG |
| 912 ## - | |
| -- | ZDB-2-SXE |
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