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Layout Techniques in MOSFETs [electronic resource] / by Salvador Pinillos Gimenez.

By: Gimenez, Salvador Pinillos [author.].
Contributor(s): SpringerLink (Online service).
Material type: materialTypeLabelBookSeries: Synthesis Lectures on Emerging Engineering Technologies: Publisher: Cham : Springer International Publishing : Imprint: Springer, 2016Edition: 1st ed. 2016.Description: XI, 69 p. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9783031020315.Subject(s): Engineering | Electrical engineering | Electronic circuits | Computers | Materials science | Surfaces (Technology) | Thin films | Technology and Engineering | Electrical and Electronic Engineering | Electronic Circuits and Systems | Computer Hardware | Materials Science | Surfaces, Interfaces and Thin FilmAdditional physical formats: Printed edition:: No title; Printed edition:: No titleDDC classification: 620 Online resources: Click here to access online
Contents:
Dedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (".
In: Springer Nature eBookSummary: This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.
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Dedication -- Acknowledgments -- Introduction -- The Origin of the Innovative Layout Techniques for MOSFETS -- Diamond MOSFET (Hexagonal Gate Geometry) -- Octo Layout Style (Octagonal Gate Shape) for MOSFET -- Ellipsoidal Layout Style for MOSFET -- Fish Layout Style (".

This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach.

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